The present invention relates to methods for manufacturing power semiconductor apparatuses used in power converters. Specifically, the present invention relates to the methods for manufacturing power semiconductor apparatuses including a main power semiconductor device and a subsidiary semiconductor device provided for the main power semiconductor device in a subordinate or additional manner.
The functions and performances of the power semiconductor apparatuses used in power converters have been improving recently. For example, power semiconductor apparatuses, which include a main semiconductor device and a subsidiary semiconductor device connected in a subordinate or additional manner onto the main semiconductor device surface, have been proposed. The subsidiary semiconductor device is formed by growing a polycrystalline semiconductor layer and by patterning the polycrystalline semiconductor layer or by implanting impurity ions into the polycrystalline semiconductor layer (see, for example, Japanese Unexamined Patent Application Publication No. Hei. 6 (1994)-117942).
A diode for temperature detection (hereinafter referred to as a “temperature detector diode”) is formed, using a polycrystalline semiconductor layer, on the surface of the power semiconductor apparatus disclosed in Japanese Unexamined Patent Application Publication No. Hei. 6 (1994)-117942 for protecting the power semiconductor apparatus against overheating. The temperature detector diode performs overheat protection utilizing the changes of the forward diode characteristics or the reverse diode characteristics thereof by the temperature. Since the forward voltage of a diode changes almost linearly with temperatures, the temperature of a power semiconductor apparatus can be detected by making a constant current flow through the temperature detector diode and by monitoring the forward voltage of the temperature detector diode.
Japanese Unexamined Patent Application Publication No. Hei. 10 (1998)-41510 discloses a semiconductor apparatus, which includes an insulated gate bipolar transistor (hereinafter referred to as an “IGBT”) and a temperature detector diode formed in the bulk section of the IGBT using a single-crystal semiconductor layer. The semiconductor apparatus disclosed in the above-referenced document utilizes the temperature dependence of the forward voltage drop across the temperature detector diode for detecting the IGBT temperature.
A semiconductor apparatus that has a chip on chip (hereinafter referred to as a “COC”) structure formed of a sensor chip bonded with a solder onto a circuit chip has been proposed (see Japanese Unexamined Patent Application Publication No. Hei. 11 (1999)-67820). A technique for connecting one of the electrodes of a diode directly to a part of an IGBT has been proposed (see Japanese Unexamined Patent Application Publication No. 2004-335719). This technique facilitates improving the performances of a semiconductor device by utilizing the forward diode characteristics or reverse diode characteristics.
Outside the field of power semiconductor apparatuses, a technique for combining a single-crystal silicon section and a polycrystalline silicon section in a liquid-crystal display apparatus driven by a thin film transistor active matrix (hereinafter referred to as a “TFT active matrix”) has been proposed (see Japanese Unexamined Patent Application Publication No. 2004-165600). The technique bonds a single-crystal silicon device in the manufacturing process thereof to an insulator substrate, thins the single crystal silicon to be a thin film, and grows polycrystalline silicon.
The technique disclose in the Japanese Unexamined Patent Application Publication No. Hei. 6 (1994)-117942 forms a polycrystalline semiconductor layer on a main power semiconductor device and, then, forms a subsidiary semiconductor device by patterning or by ion implantation, which requires many man-hours of effort. Since the subsidiary semiconductor device is manufactured using a polycrystalline semiconductor layer, the subsidiary semiconductor device manufactured as described above (hereinafter referred to as the “polycrystalline diode”) exhibits inferior characteristics, due to the crystallinity of the polycrystalline semiconductor layer, to the characteristics, which the semiconductor device manufactured using a single-crystal semiconductor layer (hereinafter referred to as a “single-crystal diode”) exhibits. Since variations are caused in the device characteristics and the built-in potential lowering is caused, it is impossible for the polycrystalline diode to successfully attain the primary targets, which the subsidiary semiconductor device is designed to attain. More specifically, when three diodes are connected in series, for example, and a predetermined current is made to flow through the diodes, the characteristics variation caused in the single-crystal diodes is suppressed within ±10 mV at 2.0 V, but a characteristics variation of ±40 mV is caused at 2.0 V in the polycrystalline diodes.
It is necessary for the technique disclosed in the Japanese Unexamined Patent Application Publication No. Hei. 10 (1998)-41510 to consider the interaction between the IGBT and the built-in diode in forming the built-in diode in the IGBT, whish also requires many man-hours of effort. Since it is necessary to form multiple diffusion layers in the main power semiconductor device and since the p-layers or n-layers diffuse outward, the impurity concentrations are lowered and the characteristics are impaired.
Since it is necessary for the technique disclosed in Japanese Unexamined Patent Application Publication No. Hei. 11 (1999)-67820 to form an electrode for soldering on the electrode plane of a main power semiconductor device, the active region area of the main power semiconductor device is reduced. Since the emitter electrode and the electrode connected to a floating layer are formed separately, it is necessary to extend the wiring between the emitter electrode and the emitter electrode pad or to extend the wiring between the electrode connected to the floating layer and the electrode pad connected to the floating layer. Since resistance is caused in the extended portion of the wiring, the electrical characteristics are impaired.
For obtaining the desired characteristics by the technique disclosed in Japanese Unexamined Patent Application Publication No. 2004-335719, it is necessary to connect a plurality of devices in series. Therefore, a wide device area is required.
Since it is necessary for the technique disclosed in Japanese Unexamined Patent Application Publication No. 2004-165600 to precisely implant hydrogen ions into a predetermined depth in a single-crystal silicon layer in advance. Therefore, the manufacturing steps are complicated. Since the device in the polycrystalline section is formed after a thick silicon single crystal is bonded, it is necessary to peel off most parts of the thick silicon single crystal. Powders are caused by the pealing off and the powders caused affect adversely the main power semiconductor device on the way of the manufacture thereof.
Although it may be considered to change the polycrystalline diode to a single-crystal diode in the technique disclosed in Japanese Unexamined Patent Application Publication No. 2004-165600, it is difficult to change the polycrystalline semiconductor layer to a single-crystal semiconductor layer. The reason for this is described below. When a silicon on insulator substrate (hereinafter referred to as a “SOI substrate”) and such a substrate are used, the area ratio of the main power semiconductor device to the subsidiary semiconductor device is large. Therefore, the ratio of the SOI section to be removed is large. Thus, the exchange of the polycrystalline diode to a single-crystal diode causes inefficiency and high manufacturing costs.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a semiconductor apparatuses, including a main semiconductor device and a subsidiary semiconductor device provided for the main semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs thereof.